What Are Registers In A Cpu
A control register is a processor register which changes or controls the full general beliefs of a CPU or other digital device. Common tasks performed past control registers include interrupt command, switching the addressing mode, paging command, and coprocessor control.
Command registers in x86 serial [edit]
CR0 [edit]
The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode, it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Annals CR0 is the 32 Flake version of the old Machine Status Word (MSW) annals. The MSW annals was expanded to the Control Register with the appearance of the i386 processor.
| Bit | Name | Full Name | Description |
|---|---|---|---|
| 0 | PE | Protected Mode Enable | If 1, arrangement is in protected mode, else organisation is in real mode |
| 1 | MP | Monitor co-processor | Controls interaction of WAIT/FWAIT instructions with TS flag in CR0 |
| two | EM | Emulation | If prepare, no x87 floating-point unit present, if clear, x87 FPU present |
| 3 | TS | Job switched | Allows saving x87 task context upon a chore switch only after x87 instruction used |
| 4 | ET | Extension type | On the 386, it allowed to specify whether the external math coprocessor was an 80287 or 80387 |
| 5 | NE | Numeric fault | Enable internal x87 floating indicate error reporting when gear up, else enables PC way x87 error detection |
| 16 | WP | Write protect | When set, the CPU can't write to read-just pages when privilege level is 0 |
| 18 | AM | Alignment mask | Alignment check enabled if AM set up, Air conditioning flag (in EFLAGS register) set, and privilege level is three |
| 29 | NW | Non-write through | Globally enables/disable write-through caching |
| 30 | CD | Cache disable | Globally enables/disable the memory cache |
| 31 | PG | Paging | If ane, enable paging and utilise the § CR3 register, else disable paging. |
CR1 [edit]
Reserved, the CPU volition throw a #UD exception when trying to access it.
CR2 [edit]
Contains a value called Page Mistake Linear Address (PFLA). When a page fault occurs, the address the programme attempted to admission is stored in the CR2 register.
CR3 [edit]
Typical employ of CR3 in accost translation with iv KiB pages
Used when virtual addressing is enabled, hence when the PG bit is set up in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the electric current chore. Typically, the upper 20 bits of CR3 get the page directory base register (PDBR), which stores the concrete address of the commencement page directory. If the PCIDE bit in CR4 is set, the lowest 12 $.25 are used for the process-context identifier (PCID).[i]
CR4 [edit]
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and car-check exceptions.
| Bit | Proper noun | Total Name | Description |
|---|---|---|---|
| 0 | VME | Virtual 8086 Mode Extensions | If set, enables support for the virtual interrupt flag (VIF) in virtual-8086 mode. |
| 1 | PVI | Protected-way Virtual Interrupts | If set, enables back up for the virtual interrupt flag (VIF) in protected way. |
| ii | TSD | Fourth dimension Stamp Disable | If set, RDTSC teaching tin can just exist executed when in ring 0, otherwise RDTSC tin can be used at whatever privilege level. |
| 3 | DE | Debugging Extensions | If set up, enables debug annals based breaks on I/O space access. |
| four | PSE | Page Size Extension | If unset, page size is four KiB, else page size is increased to 4 MiB If PAE is enabled or the processor is in x86-64 long mode this bit is ignored.[2] |
| five | PAE | Physical Accost Extension | If gear up, changes page table layout to translate 32-bit virtual addresses into extended 36-bit physical addresses. |
| 6 | MCE | Machine Cheque Exception | If fix, enables motorcar check interrupts to occur. |
| vii | PGE | Folio Global Enabled | If ready, address translations (PDE or PTE records) may exist shared between address spaces. |
| 8 | PCE | Functioning-Monitoring Counter enable | If set, RDPMC can be executed at any privilege level, else RDPMC can merely be used in ring 0. |
| 9 | OSFXSR | Operating system back up for FXSAVE and FXRSTOR instructions | If fix, enables Streaming SIMD Extensions (SSE) instructions and fast FPU save & restore. |
| x | OSXMMEXCPT | Operating Organisation Back up for Unmasked SIMD Floating-Indicate Exceptions | If set, enables unmasked SSE exceptions. |
| xi | UMIP | User-Mode Didactics Prevention | If prepare, the SGDT, SIDT, SLDT, SMSW and STR instructions cannot be executed if CPL > 0.[1] |
| 12 | LA57 | 57-Bit Linear Addresses | If set, enables 5-Level Paging.[three] [four] : 2–xviii |
| 13 | VMXE | Virtual Machine Extensions Enable | meet Intel VT-10 x86 virtualization. |
| 14 | SMXE | Safer Mode Extensions Enable | encounter Trusted Execution Technology (TXT) |
| xvi | FSGSBASE | Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. | |
| 17 | PCIDE | PCID Enable | If prepare, enables process-context identifiers (PCIDs). |
| 18 | OSXSAVE | XSAVE and Processor Extended States Enable | |
| 20 | SMEP [5] | Supervisor Way Execution Protection Enable | If set, execution of code in a college band generates a fault. |
| 21 | SMAP | Supervisor Mode Admission Prevention Enable | If set, access of data in a higher ring generates a error.[6] |
| 22 | PKE | Protection Primal Enable | See Intel 64 and IA-32 Architectures Software Developer's Manual. |
| 23 | CET | Command-flow Enforcement Technology | If set, enables command-flow enforcement engineering.[4] : 2–19 |
| 24 | PKS | Enable Protection Keys for Supervisor-Mode Pages | If set, each supervisor-mode linear accost is associated with a protection key when four-level or 5-level paging is in use.[iv] : ii–xix |
CR5-7 [edit]
Reserved, aforementioned instance as CR1.
Additional Command registers in x86-64 series [edit]
EFER [edit]
Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to let enabling the SYSCALL/SYSRET instruction, and later for entering and exiting long mode. This annals becomes architectural in AMD64 and has been adopted by Intel as IA32_EFER. Its MSR number is 0xC0000080.
| Scrap | Purpose |
|---|---|
| 0 | SCE (Organization Phone call Extensions) |
| i | DPE (AMD K6 only: Information Prefetch Enable) |
| 2 | SEWBED (AMD K6 only: Speculative EWBE# Disable) |
| 3 | GEWBED (AMD K6 only: Global EWBE# Disable) |
| four | L2D (AMD K6 only: L2 Cache Disable) |
| v-7 | Reserved, Read every bit Zero |
| 8 | LME (Long Style Enable) |
| ix | Reserved |
| 10 | LMA (Long Mode Active) |
| eleven | NXE (No-Execute Enable) |
| 12 | SVME (Secure Virtual Machine Enable) |
| 13 | LMSLE (Long Way Segment Limit Enable) |
| fourteen | FFXSR (Fast FXSAVE/FXRSTOR) |
| 15 | TCE (Translation Cache Extension) |
| 16–63 | Reserved |
CR8 [edit]
CR8 is a new register accessible in 64-fleck mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR).[2]
The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from i to 15, with priority-class ane being the lowest and priority-grade xv the highest. CR8 uses the four depression-order bits for specifying a chore priority and the remaining 60 bits are reserved and must be written with zeros.
Arrangement software tin can utilize the TPR annals to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority form of 9 or less, while allowing all interrupts with a priority grade of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with fifteen (1111b) disables all external interrupts.
The TPR is cleared to 0 on reset.
XCR0 and XSS [edit]
XCR0, or Extended Control Annals 0, is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is likewise used with some features to enable or disable the processor's ability to execute their respective instructions. It can be accessed using the privileged XSETBV and nonprivileged XGETBV instructions.[vii]
| Bit | Purpose |
|---|---|
| 0 | X87 (x87 FPU/MMX State, note, must be 'i') |
| 1 | SSE (XSAVE characteristic set enable for MXCSR and XMM regs) |
| 2 | AVX (AVX enable, and XSAVE feature set can be used to manage YMM regs) |
| 3 | BNDREG (MPX enable, and XSAVE feature set tin can be used for BND regs) |
| four | BNDCSR (MPX enable, and XSAVE feature set can be used for BNDCFGU and BNDSTATUS regs) |
| 5 | opmask (AVX-512 enable, and XSAVE feature set can be used for AVX opmask, AKA thousand-mask, regs) |
| 6 | ZMM_hi256 (AVX-512 enable, and XSAVE feature set can be used for upper-halves of the lower ZMM regs) |
| 7 | Hi16_ZMM (AVX-512 enable, and XSAVE feature set can exist used for the upper ZMM regs) |
| 8 | Reserved |
| nine | PKRU (XSAVE feature set can be used for PKRU annals, which is function of the protection keys machinery.) |
| 10 | Reserved (must be '0') |
| 11 | Command-flow Enforcement Technology (CET) User State |
| 12 | Control-flow Enforcement Technology (CET) Supervisor State |
| 13–63 | Reserved (must exist '0') |
In that location is also the IA32_XSS MSR, which is located at address 0DA0h. The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the information they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE didactics would only store X87 state, while the privileged XSAVES would store both X87 and PT states. Because it is an MSR, it tin be accessed using the RDMSR and WRMSR instructions.
| Scrap | Purpose |
|---|---|
| 0–vii | Reserved; must be 0. |
| eight | PT (Enables the saving and loading of ix Processor Trace MSRs.) |
| 9–12 | Reserved; must exist 0. |
| 13 | HDC (Enables the saving and loading of the IA32_PM_CTL1 MSR.) |
| 14–63 | Reserved; must exist 0. |
Come across besides [edit]
- Full general-purpose annals
- Test annals
- Model-specific annals
- Debug register
- Flag byte
- Status register
References [edit]
- ^ a b Intel Corporation (2016). "four.10.1 Process-Context Identifiers (PCIDs)". Intel 64 and IA-32 Architectures Software Developer'due south Transmission (PDF). Vol. 3A: Organization Programming Guide, Part 1.
- ^ a b "AMD64 Architecture Programmer'south Manual Book ii: Organisation Programming" (PDF). AMD. September 2012. p. 127 & 130. Retrieved 2017-08-04 .
- ^ "5-Level Paging and 5-Level EPT" (PDF). Intel. May 2017. p. 16. Retrieved 2018-01-23 .
- ^ a b c "Intel® 64 and IA-32 Architectures Software Programmer's Manual" (PDF). Intel® Corporation. 2021-06-28. Retrieved 2021-09-21 .
- ^ Fischer, Stephen (2011-09-21). "Supervisor Mode Execution Protection" (PDF). NSA Trusted Calculating Conference 2011. National Briefing Services, Inc. Archived from the original (PDF) on 2016-08-03. Retrieved 2017-08-04 .
- ^ Anvin, H. Peter (2012-09-21). "x86: Supervisor Way Access Prevention". LWN.cyberspace. Retrieved 2017-08-04 .
- ^ "Chapter 13, Managing State Using The Xsave Characteristic Set" (PDF). Intel(R) 64 and IA-32 Architectures Software Developer'southward Manual, Volume ane: Basic Architecture. Intel Corporation (2019). Retrieved 23 March 2019.
External links [edit]
- Intel 64 and IA-32 Architectures Developer'due south Manual: Vol. 3A
- Intel 64 and IA-32 Architectures Software Developer Manuals
- Tech Docs: AMD64
- Wyatt's World: Nifty Open the Pentium III (1999-05-28)
What Are Registers In A Cpu,
Source: https://en.wikipedia.org/wiki/Control_register
Posted by: freemanpinhould1981.blogspot.com
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